Dr. R. Jaikumar has received his B.E in ECE from Mahendra Engineering College in 2006, ME VLSI Design from Anna University Regional Campus, Coimbatore in 2009 and Ph.D. in Information and Communication Technology, Anna University in 2020. He has around 10 years of teaching experience.
| Experience (Industry /Teaching) | 10 Years |
|---|---|
| Area of Research Specialization | VLSI Design, IoT |
| Research/Funding Project handled(Count) | Nil |
| Publication (National /International Journal and Conference) | 8 |
| Any other (related to research) | Nil |
| S.No | Research/Project handled-List |
|---|---|
| NIL | |
| S.No. | Publication (National /International Journal) |
|---|---|
| 1 | R.Gayathri,R.Lavanya, Dr.R.Jaikumar “Vehicle monitoring and controlling using multi-sensors in ad-hoc networks”, Vol.8, Issue.6, June 2020. |
| 2 | Jaikumar.R and Poongodi.P (2018), ‘Noise Measurement in High Speed Domino Pseudo CMOS Keeper’, Measurement and Control, SAGE Journals, (SCIE and SCOPUS indexed), Volume 52, Issue 1-2, pp. 20-27, ISSN : 00202940, Impact Factor: 0.878. |
| 3 | Jaikumar.R and Poongodi.P (2018), ‘A new low power design technique for Noise tolerant CMOS dynamic logic circuits’, International Journal of Pure and Applied Mathematics (SCOPUS indexed), Volume 119, No. 17, 397-413. |
| 4 | Lavanya.R, Karpagam.M and Jaikumar.R (2017), ‘A Comparative Study on the Implementation of Block Cipher Algorithms on FPGA’, International Journal of Scientific Research in Science and Technology (UGC Approved), Vol.3, Issue 8,(Impact Factor :3.6) |
| 5 | Jaikumar.R, Karpagam.M, and Lavanya.R (2015), ‘A Novel Approach To Implement High Speed Squaring Circuit Using Ancient Vedic Mathematics Techniques’, International Journal of Applied Engineering Research (SCOPUS indexed), 10(67):1-6. |
| 6 | Jaikumar.R, Poongodi.P and Lavanya.R (2015), ‘Implementation of high speed arithmetic logic using ancient Vedic mathematics techniques” in ICTACT journal on microelectronics, Vol:1, Issue :1. |
| 7 | Jaikumar.R, Poongodi.P and Lavanya.R, (2017), ‘Reducing Power Consumption Using Positive Feedback Adiabatic Logic In 4-Bit Ripple Carry Adder’, Proceedings of IEEE International Conference on Science, Technology, Engineering and Management, Kalaignar Karunanidhi Institute of Technology, March 3-4,2017. |
| 8 | Lavanya.R, Karpagam. M and Jaikumar.R (2017), ‘A Comparative Analysis of DPA Resistant Logic for Design of Low Power Adder Circuits’, Proceedings of IEEE International Conference on Innovations in Green Energy and Health Care Technologies, NGP Institute of Technology,16 – 18 March, 2017. |
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